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A novel dynamic power cutoff technology (DPCT) for active leakage reduction in deep submicron VLSI CMOS circuits
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Yu, Baozhen. A novel dynamic power cutoff technology (DPCT) for active leakage reduction in deep submicron VLSI CMOS circuits. Retrieved from https://doi.org/doi:10.7282/T30Z73PM

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Uniform TitleA novel dynamic power cutoff technology (DPCT) for active leakage reduction in deep submicron VLSI CMOS circuits
NameYu, Baozhen (author); Bushnell, Michael (chair); Marsic, Ivan (internal member); Zhang, Yanyong (internal member); Sheng, Kuang (internal member); Agrawal, Vishwani (outside member); Rutgers University; Graduate School - New Brunswick
Date Created2007
Other Date2007 (degree)
SubjectElectrical and Computer Engineering, Electronic circuits
Extentxiii, 101 pages
DescriptionDue to the exponential increase of subthreshold and gate leakage currents with technology scaling, leakage power is increasingly significant in CMOS circuits as the technology scales down. The leakage power is as much as 50% of the total power in the 90nm technology and is becoming dominant in more advanced CMOS technologies with smaller feature sizes. Also, the leakage in active mode is significantly larger due to the higher die temperature in active mode. Although many leakage reduction techniques have been proposed, most of them can only reduce the circuit leakage power in standby mode.
In this thesis, we present a novel active leakage power reduction technique using dynamic power cutoff, called the dynamic power cutoff technique (DPCT). To reduce the active leakage power, we target the idle part of the circuit when it is in active mode. First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. The power of each gate is only turned on during a small timing window within each clock cycle, which results in significant active leakage power savings. Standby leakage can also be reduced by turning off the power connections of all gates all of the time once the circuit is idle. This technique also reduces dynamic power and short-circuit power by reducing the circuit glitches.
Experimental results on ISCAS '85 benchmark circuits at the logic level modeled using 70nm Berkeley Predictive Models show up to 90% of active leakage, 99% of standby leakage, up to 54% of dynamic, and up to 72% of total power savings. DPCT can also reduce the maximal voltage drop on the power grid by more than 30% on average. With process variations, the average total power and active leakage power savings will be reduced by 12.7% and 14.8%, respectively. In spite of that, DPCT still gives excellent power savings, which are 73.6% of active leakage power and 34.7% of total power under process variations. We also implemented the layouts of a 16-bit multiplier and a c432 using DPCT. The experimental results for the layout designs confirmed the effectiveness of DPCT in physical level design.
NotePh.D.
NoteIncludes bibliographical references (p. 94-100).
Genretheses, ETD doctoral
Persistent URLhttps://doi.org/doi:10.7282/T30Z73PM
LanguageEnglish
CollectionGraduate School - New Brunswick Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.
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